Semiconductor device and manufacturing method thereof

ABSTRACT

An interlayer insulating film ( 104 ) that is formed on a substrate( 101 ) so as to cover TFTs( 102, 103 ) is planarized by mechanical polishing that is typified by CMP. Pixel electrodes ( 106, 107 ) are formed on the interlayer insulating film( 104 ) and an insulating layer( 108 ) is formed so as to cover the pixel electrodes. The insulating layer( 108 ) is planarized by second mechanical polishing so that the surfaces of the pixel electrodes become flush with those of resulting buried insulating layers( 112, 113 ). Since the pixel electrode surfaces have no steps, such problems as alignment failures of a liquid crystal material and a contrast reduction due to diffused reflection of light can be prevented.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a manufacturing method of aliquid crystal display device (LCD), in particular, an active matrixliquid crystal display device (hereinafter abbreviated as AM-LCD) thatuses a semiconductor thin film. The invention can be applied to anelectro-optical device having such a display device.

[0003] 2. Description of the Related Art

[0004] In this specification, the term “semiconductor device” meansevery device that functions by using a semiconductor. Therefore, each ofthe above-mentioned display device and electro-optical device isincluded in the scope of the semiconductor device. However, in thisspecification, the terms “display device” and “electro-optical device”are used for the sake of discrimination.

[0005] In recent years, projectors or the like that use an AM-LCD as aprojection-type display have been developed extensively. Further, thedemand for AM-LCDs as direct-view displays for mobile computers andvideo cameras is now increasing.

[0006]FIGS. 2A and 2B schematically show the configuration of a pixelmatrix circuit in a conventional AM-LCD. The pixel matrix circuit, whichconstitutes an image display area of the AM-LCD, is a circuit in whichthin-film transistors (TFTs) for controlling electric fields applied toa liquid crystal are arranged in matrix form.

[0007]FIG. 2A is a top view of the pixel matrix circuit. The regionsthat are enclosed by a plurality of gate lines 201 extending in thehorizontal direction and a plurality of source lines 202 extending inthe vertical direction are pixel regions. TFTs 203 are formed at therespective intersections of the gate lines 201 and the source lines 202.Pixel electrodes 204 are connected to the respective TFTs.

[0008] Thus, the pixel matrix circuit consists of a plurality of pixelregions that are enclosed by the gate lines 201 and the source lines 202and are thereby arranged in matrix form, and each pixel region isprovided with a TFT 203 and a pixel electrode 204.

[0009]FIG. 2B shows a sectional structure of the pixel matrix circuit.In FIG. 2B, reference numeral 205 denotes a substrate having aninsulating surface and numerals 206 and 207 denote pixel TFTs formed onthe substrate 205. The pixel TFTs 206 and 207 correspond to the TFTs 203in FIG. 2A.

[0010] Pixel electrodes 208 and 209, which correspond to the pixelelectrodes 204 in FIG. 2A, are connected to the respective pixel TFTs206 and 207. Usually, the pixel electrodes 208 and 209 are obtained bypatterning a single metal thin film.

[0011] Therefore, the pixel matrix circuit having the conventionalstructure necessarily includes electrode boundary portions (hereinafterreferred to simply as boundary portions) 210 and 211 between the pixelelectrodes 208, 209, etc.; there necessarily occur steps correspondingto the film thickness of the pixel electrodes 208 and 209. The steps ofthis type may cause alignment failures of a liquid crystal material,leading to a disordered display image. Further, diffused reflection atthe step portions of incident light may deteriorate the contrast orreduce the efficiency of light utilization.

[0012] As seen from FIG. 2B, above the semiconductor elements and theintersections of the wiring lines, the pixel electrodes 208 and 209 areformed so as to reflect their shapes. The steps of this type may alsocause the above-mentioned problems.

[0013] In particular, the above problems appear more remarkably inprojection-type displays for projectors and the like, because an imageof a small (about 1 to 2 inches), very-high-resolution display isprojected in an enlarged manner.

[0014] Conventionally, to deal with the above problems, the contrastratio is increased by shielding regions where an image may be disorderedwith a black mask (or a black matrix). In recent years, because thedevice miniaturization has advanced and hence a high degree ofcontrollability of shield regions is required to provide a largeaperture ratio, a configuration in which a black mash is formed on aTFT-side substrate is the mainstream.

[0015] However, forming a black mash on a TFT-side substrate causesvarious problems such as an increased number of patterning steps, anincrease in parasitic capacitance, and a decrease in aperture ratio.Therefore, a technique for securing a high contract ratio withoutcausing above-mentioned problems is now desired.

SUMMARY OF THE INVENTION

[0016] The present invention has been made in view of above circumstanceand therefore, an object of the present invention is to solve the aboveproblems in the art and to thereby enable, with a simple means,formation of a very-high-resolution AM-LCD.

[0017] According to a first aspect of the invention, there is provided amanufacturing method of a semiconductor device, comprising the steps ofplanarizing an insulating film formed on a substrate having aninsulating surface; forming a plurality of electrodes on the insulatingfilm; forming an insulating layer so as to cover the plurality ofelectrodes; and planarizing surfaces of the plurality of electrodes anda surface of the insulating layer so that they become flush with eachother, thereby filling boundary portions between the plurality ofelectrodes with the insulating layer.

[0018] There is also provided a manufacturing method of a semiconductordevice having a first substrate, a second, transparent substrate, and aliquid crystal layer held between the first and second substrates,comprising the steps of planarizing an insulating film formed on thefirst substrate; forming striped electrodes on the insulating film;forming an insulating layer so as to cover the striped electrodes; andplanarizing surfaces of the striped electrodes and a surface of theinsulating layer so that they become flush with each other, therebyfilling boundary portions between the striped electrodes with theinsulating layer.

[0019] There is also provided a manufacturing method of a semiconductordevice, comprising the steps of forming a plurality of semiconductorelements on a substrate having an insulating surface; forming aninterlayer insulating film; planarizing the interlayer insulating film;forming pixel electrodes that are electrically connected to therespective semiconductor elements on the interlayer insulating film;forming an insulating layer so as to cover the pixel electrodes; andplanarizing surfaces of the pixel electrodes and a surface of theinsulating layer so that they become flush with each other, therebyfilling boundary portions between the pixel electrodes with theinsulating layer.

[0020] There is further provided a manufacturing method of asemiconductor device having a substrate that has a plurality ofsemiconductor elements arranged in matrix form and a plurality of pixelelectrodes connected to the respective semiconductor elements, and aliquid crystal layer held on the substrate, comprising the steps offorming an interlayer insulating film; planarizing the interlayerinsulating film; forming pixel electrodes that are electricallyconnected to the respective semiconductor elements on the interlayerinsulating film; forming an insulating layer so as to cover the pixelelectrodes; and planarizing surfaces of the pixel electrodes and asurface of the insulating layer so that they become flush with eachother, thereby filling boundary portions between the pixel electrodeswith the insulating layer.

[0021] According to a second aspect of the invention, there is provideda semiconductor device comprising a plurality of electrodes formed on asubstrate having an insulating surface; a DLC film covering theplurality of electrodes; and an insulating layer buried in boundaryportions of the plurality of electrodes.

[0022] There is also provided a semiconductor device comprising a firstsubstrate; a second, transparent substrate; a liquid crystal layer heldbetween the first and second substrates; striped electrodes formed oneach of the first and second substrates; a DLC film covering the stripedelectrodes; and an insulating layer buried in boundary portions of thestriped electrodes.

[0023] There is also provided a semiconductor device comprising aplurality of semiconductor elements formed in matrix form on a substratehaving an insulating surface; a plurality of pixel electrodes connectedto the respective semiconductor elements; a DLC film covering the pixelelectrodes; and an insulating layer buried in boundary portions of thepixel electrodes.

[0024] There is further provided a semiconductor device comprising asubstrate having a plurality of semiconductor elements arranged inmatrix form and a plurality of pixel electrodes connected to therespective semiconductor elements; a liquid crystal layer held on thesubstrate; a DLC film covering the pixel electrodes; and an insulatinglayer buried in boundary portions of the pixel electrodes.

[0025] Still according to the second aspect of the invention, there isprovided a manufacturing method of a semiconductor device, comprisingthe steps of forming a plurality of electrodes on a substrate having aninsulating surface; forming a DLC film to cover a plurality ofelectrodes; forming an insulating layer on the DLC film; and planarizingthe insulating layer so that a surface of the DLC film and a surface ofthe insulating layer become flush with each other, thereby fillingboundary portions of the plurality of electrodes with the insulatinglayer.

[0026] There is also provided a manufacturing method of a semiconductordevice having a first substrate, a second, transparent substrate, and aliquid crystal layer held between the first and second substrates,comprising the steps of forming striped electrodes on the firstsubstrate; forming a DLC film to cover the striped electrodes; formingan insulating layer on the DLC film; and planarizing the insulatinglayer so that a surface of the DLC film and a surface of the insulatinglayer become flush with each other, thereby filling boundary portions ofthe striped electrodes with the insulating layer.

[0027] There is also provided a manufacturing method of a semiconductordevice, comprising the steps of forming a plurality of semiconductorelements on a substrate having an insulating surface; forming aplurality of pixel electrodes that are electrically connected to therespective semiconductor elements; forming a DLC film to cover the pixelelectrodes; forming an insulating layer on the DLC film; and planarizingthe insulating layer so that a surface of the DLC film and a surface ofthe insulating layer become flush with each other, thereby fillingboundary portions of the pixel electrodes with the insulating layer.

[0028] There is further provided a manufacturing method of asemiconductor device having a substrate that has a plurality ofsemiconductor elements arranged in matrix form and a plurality of pixelelectrodes connected to the respective semiconductor elements, and aliquid crystal layer held on the substrate, comprising the steps offorming a DLC film to cover the pixel electrodes; forming an insulatinglayer on the DLC film; and planarizing the insulating layer so that asurface of the DLC film and a surface of the insulating layer becomeflush with each other, thereby filling boundary portions of theplurality of the pixel electrodes with the insulating layer.

[0029] In the above description of the invention, the term DLC is anabbreviation of “diamond-like carbon.” A DLC film is therefore a thinfilm that is made only or mainly of carbon and that exhibitsdiamond-like physical properties such as high hardness. This material isalso called i-carbon and mainly has sp³ bonds.

[0030] The hardness (Vickers hardness) of a DLC film is as high as 2,000kg/mm² or more and its friction coefficient is 0.4 or less. Therefore,DLC films are used as protection films and lubrication films. However,if the hydrogen content is excessively large, a DLC film becomes toosoft to be used in the invention.

[0031] A DLC film exhibits a characteristic feature in Raman data. FIG.18 shows Raman data of a DLC film used in the invention, in which thevertical axis represents relative intensity. A measurement was conductedin the air at the room temperature by using an Ar+ laser (laser beamdiameter: 1 μm; output power: 1.0 mW; slit width: 100 μm). Theaccumulation time was 300 sec×2.

[0032] As seen from FIG. 18, a DLC film has a broad Raman spectrumextending on both sides of a peak at about 1,550 cm⁻¹. The fact that theRaman spectrum is asymmetrical with respect to the peak 1,550 cm⁻¹ isalso a feature of a DLC film.

[0033] Raman data of diamond has a sharp peak at about 1,330 cm⁻¹ andhence is easily distinguished from that of a DLC film. Further, a carbonfilm that is rendered soft due to loss of a crystal structure (regardedas a different material than a DLC film) has two Raman peaks or no clearRaman peak and hence can easily be distinguished from a DLC film.

[0034] In connection with the above description of the invention, atypical example of the liquid crystal layer holding state is such that aliquid crystal layer is held between a substrate (first substrate)having a plurality of pixel electrodes and an opposed substrate (secondsubstrate) that confronts the first substrate. Where a PDLC (polymerdispersion liquid crystal) is used as a liquid crystal layer, there mayoccur a case that the second substrate is not necessary, because theliquid crystal layer itself is rendered in a solid state.

[0035] The typical example of the semiconductor element is a thin-filmtransistor (TFT). In addition, the semiconductor element may be aninsulated-gate field-effect transistor (IGFET), a thin-film diode, anMIM (metal-insulator-metal) element, a varistor element, or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036]FIGS. 1A to 1C are sectional views for brief description of thepresent invention;

[0037]FIGS. 2A and 2B show the configuration of a conventional pixelmatrix circuit;

[0038]FIGS. 3A to 3D and 4A to 4C show a process of manufacturing areflection-type LCD according to a first embodiment of the invention;

[0039]FIGS. 5A to 5C show a process of manufacturing a transmission typeLCD according to a second embodiment of the invention;

[0040]FIG. 6 is a top view of a pixel matrix circuit according to thefirst embodiment;

[0041]FIG. 7 is a top view of a pixel matrix circuit according to thesecond embodiment;

[0042]FIG. 8 shows a structure of an active matrix substrate accordingto a fourth embodiment of the invention;

[0043]FIG. 9 shows another structure of an active matrix substrateaccording to the fourth embodiment;

[0044]FIGS. 10A to 10C are sectional views for brief description of theinvention;

[0045]FIGS. 11A to 11D and 12A to 12C show a process of manufacturing areflection type LCD according to a fifth embodiment of the invention;

[0046]FIGS. 13A to 13C show a process of manufacturing atransmission-type LCD according to a sixth embodiment of the invention;

[0047]FIG. 14 is a top view of a pixel matrix circuit according to thefifth embodiment;

[0048]FIG. 15 is a top view of a pixel matrix circuit according to thesixth embodiment;

[0049]FIG. 16 shows a structure of an active matrix substrate accordingto an eighth embodiment of the invention;

[0050]FIG. 17 shows another structure of an active matrix substrateaccording to eighth embodiment;

[0051]FIG. 18 shows Raman data of a DLC film;

[0052]FIGS. 19A and 19B show configurations of projectors according to atwelfth embodiment of the invention; and

[0053]FIGS. 20A to 20F show examples of application products accordingto a thirteenth embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] First, the present invention will be described briefly withreference to FIGS. 1A to 1C and 10A to 10C.

[0055] In FIG. 1A, reference numeral 101 denotes a substrate having aninsulating substrate, and numerals 102 and 103 denote first and secondpixel TFTs, respectively, formed on the substrate 101. The first andsecond pixel TFTs 102, 103 are covered with an interlayer insulatingfilm 104, which is an insulating film for electrically insulating thepixel TFTs 102 and 103 from pixel electrodes that will be formed later.

[0056] A first feature of a first aspect of the invention is that theinterlayer insulating film 104 that has been deposited so as to bethicker than a necessary thickness is subjected to a planarization step(particularly by mechanical polishing). The interlayer insulating film104 polishing step, which will be described later, will play animportant role in forming pixel electrodes later. In FIG. 1A, a brokenline 105 represents the shape of the interlayer insulating film 104before being subjected to the polishing step and indicates that surfaceasperities of the interlayer insulating film 104 are removed, i.e., thesurface is planarized, by the mechanical polishing step.

[0057] A typical example of the mechanical polishing is the CMP(chemical mechanical polishing) technique in which the surface of a thinfilm is planarized by chemical etching with a liquid chemical andmechanical polishing with an abrasive (abrasive grains).

[0058] Other than the mechanical polishing, an etch back techniqueutilizing dry etching may be used. Although the etch back technique isinferior to the CMP technique in flatness attained, it is advantageousin that no additional apparatus is needed and that no particles (dust)occur during processing.

[0059] Then, a metal thin film (not shown) is formed on the planarizedinterlayer insulating film 104 and then patterned into pixel electrodes106 and 107 (see FIG. 1B). In the first aspect of the invention, sincethe interlayer insulating film 104 is planarized, the pixel electrodes106 and 107 thus formed have extremely flat surfaces.

[0060] The pixel electrodes 106 and 107 are connected to the respectivepixel TFTs 102 and 103 via contact holes. The pixel electrodes 106 and107 are then covered with an insulating layer 108. At this time, bydepositing the insulating film 108 at a larger thickness than anecessary value, boundary portions 109 and 110 are filled in completely.

[0061] A second feature of the first aspect of the invention is that theinsulating layer 108 is mechanically polished to leave parts of theinsulating layer 108 only in the boundary portions 109 and 110; buriedinsulating layers 112 and 113 are formed as shown in FIG. 1C. A brokenline 111 shown FIG. 1B represents the shape of the insulating layer 108before being subjected to the polishing step and indicates how theinsulating layer 108 is ground away by the mechanical polishing step.

[0062] The surfaces of the pixel electrodes 106 and 107 appear as theinsulating layer 108 is polished in the above manner. Although the stateof FIG. 1C can be obtained even if the polishing is stopped at thisstage, it is effective to continue the polishing to also planarize thesurfaces of the pixel electrodes 106 and 107. In this case, theconditions of the polishing may be modified (for instance, using finerabrasive grains) when necessary to render the surfaces of the pixelelectrodes 106 and 107 in best conditions.

[0063] In the final state shown in FIG. 1C, the boundary portions 109and 110 formed between the pixel electrodes 106, 107, etc. arecompletely filled in by the buried insulating layers 112 and 113. Thesurfaces of the pixel electrodes 106 and 107 are flush with the surfacesof the buried insulating layers 112 and 113.

[0064] In this state, as mentioned above, the first feature of the firstaspect of the invention, i.e., the interlayer insulating film 104polishing step, plays an important role. This will be described below.

[0065] For example, if the interlayer insulating film 104 polishing stephad not been executed, the shapes of the pixel electrodes 106 and 107and the insulating film 108 would reflect the shape represented bynumeral 105 to a large extent. In general, to increase the apertureratio, the boundary portions 109 and 110 are necessarily formed on therespective TFTs 102 and 103 (on the source lines). Therefore, theboundary portions 109 and 110 would become higher than the effectivepixel electrode surfaces (the flattest portions of the pixel electrodesurfaces that do not coextend with the TFTs 102 and 103 nor the wiringlines).

[0066] Therefore, the portions of the pixel electrode surfaces rightabove the TFTs 102 and 103 would be exposed first as the insulatinglayer 108 is mechanically polished. When the effective pixel electrodesurfaces are polished, the portions of the pixel electrode surfacesright above the TFTs 102 and 103 and the buried insulating layers 112and 113 would have been polished considerably; it would be difficult toperform polishing uniformly.

[0067] It is conceivable to planarize the surface, i.e., remove theasperities that are caused by the TFTs 102 and 103 etc., by depositingthe interlayer insulating film 104 at a larger thickness than anecessary value. However, merely depositing such a thick interlayerinsulating film 104 necessarily leaves not a little surface asperitysuch as undulation. To remove such undulation, it is necessary to formthe insulating layer 108 at a larger thickness than a necessary valueand to execute the mechanical polishing step for a longer time, whichwill cause problems such as a decrease in throughput and an increase ofparticles generated.

[0068] As described above, planarizing the interlayer insulating film bythe mechanical polishing step before formation of the pixel electrodesis a very effective means. That is, although the most important objectof the first aspect of the invention is to obtain the state of FIG. 1Cby the polishing step of FIG. 1B, the first aspect of the invention isalso characterized by the polishing step of FIG. 1A which is executed toallow the polishing step of FIG. 1B to be executed efficiently.

[0069] Then, as shown in FIG. 1C, the gaps (boundary portions) betweenthe pixel electrodes are filled in by the buried insulating layers, toeliminate unnecessary steps. As a result, the invention can provide avery-high-resolution AM-LCD that is free of such problems as alignmentfailures of a liquid crystal material and diffused reflection of lightat step portions which problems are associated with conventionalAM-LCDs.

[0070] Next, a second aspect of the invention will be described below.In FIG. 10A, reference numeral 1001 denotes a substrate having aninsulating surface and numerals 1002 and 1003 denote pixel TFTs formedon the substrate 1001. Pixel electrodes 1005 and 1006 are formed on therespective pixel TFTs 1002 and 1003 with an interlayer insulating film1004 interposed in between. The pixel electrodes 1005 and 1006 areelectrically connected to the respective pixel TFTs 1002 and 1003, andare electrically insulated from each other at boundary portions 1007 and1008.

[0071] The feature of the second aspect of the invention is that a DLCfilm 1009 of 10 to 50 nm in thickness is formed so as to cover the pixelelectrodes 1005 and 1006. After the state of FIG. 10A is obtained, aninsulating layer 1010 for filling in the boundary portions 1007 and 1008of the pixel electrodes 1005 and 1006 over the pixel electrodes 1005 and1006. If the insulating layer 1010 is a light interruptive thin film(for instance, a light absorption layer), it can serve as a black mask.

[0072] Then, as shown in FIG. 10B, the insulating layer 1010 issubjected to a planarization process. Mechanical polishing is a typical,effective method. A typical example of mechanical polishing is the CMP(chemical mechanical polishing) technique in which the surface of a thinfilm is planarized by chemical etching with a liquid chemical andmechanical polishing with an abrasive (abrasive grains), and which canproduce a superior flat surface.

[0073] Other than the mechanical polishing, an etch back techniqueutilizing dry etching may be used. Although the etch back technique isinferior to the CMP technique in flatness attained, it is advantageousin that no additional apparatus is needed and that no particles (dust)occur during processing.

[0074] In the second aspect of the invention, the surface of the DLCfilm 1009 appears as the polishing of the insulating layer 1010proceeds. Since the DLC film 1009 is very high in hardness, themechanical polishing does not proceed any further. That is, theplanarization step is completed at the time point that the DLC film hasappeared.

[0075] As a result of the above planarization step, buried insulatinglayers 1011 and 1012 are formed as shown in FIG. 10C. A broken line inFIG. 10B represents the shape of the insulating layer 1010 before beingsubjected to the polishing step, and indicates how the insulating layer1010 is ground away by the mechanical polishing step.

[0076] In the final state shown in FIG. 10C, the boundary portions 1007and 1008 formed between the pixel electrodes are completely filled in bythe buried insulating layers 1011 and 1012. The surfaces of the pixelelectrodes 1005 and 1006 are flush with the surfaces of the buriedinsulating layers 1011 and 1012.

[0077] As described above, according to the second aspect of theinvention, the boundary portions between the pixel electrodes are filledin by the buried insulating layers, whereby unnecessary steps areeliminated. As a result, there can be provided a very-high-resolutionAM-LCD that is free of such problems as alignment failures of a liquidcrystal material and diffused reflection of light at step portions whichproblems are associated with conventional AM-LCDs.

[0078] Embodiment 1

[0079] In this embodiment, an example process of manufacturing a pixelmatrix circuit of a reflection-type LCD by utilizing the first aspect ofthe invention will be described with reference to FIGS. 3A to 3D and 4Ato 4C. Since the invention is directed to the technique relating toplanarization of pixels, the TFT structure itself is not limited to thatin this embodiment.

[0080] First, a substrate 301 having an insulating surface is prepared.In this embodiment, a silicon oxide film as an undercoat film is formedon a glass substrate. Then, active layers 302 to 304 that arecrystalline silicon films are formed on the substrate 301. Although onlythree TFTs will be described in this embodiment, actually million ormore TFTs are formed in a pixel matrix circuit.

[0081] In this embodiment, a crystalline silicon film is obtained bythermally crystallizing an amorphous silicon film. The crystallinesilicon film is patterned into the active layers 302 to 304 by anordinary photolithography method. In this embodiment, a catalyst element(nickel) for accelerating crystallization is added in thecrystallization step. This technique is described in detail in JapaneseUnexamined Patent Publication No. Hei. 7-130652.

[0082] Then, a 150-nm-thick silicon oxide film is formed as a gateinsulating film 305. An aluminum film (not shown) containing scandium at0.2 wt % is formed thereon and patterned into island-like patterns asstarting members of gate electrodes.

[0083] At this stage, in this embodiment, a technique disclosed inJapanese Unexamined Patent Publication No. Hei. 7-135318 is utilized.For details, refer to this publication.

[0084] First, anodization is performed in a 3%-aqueous solution ofoxalic acid in a state that the resist mask that was used in thepatterning is left on the island-like patterns. A platinum electrode isused as the cathode, the formation current is set at 2 to 3 mA, and thefinal voltage is set at 8 V. In this manner, porous anodic oxide films306 to 308 are formed.

[0085] After the resist mask is removed, anodization is again performedin a solution obtained by neutralizing 3%-ethylene glycol solution oftartaric acid with aqueous ammonia. The formation current and the finalvoltage may be set at 5 to 6 mA and 100 V, respectively. Dense anodicoxide films 309 to 311 are thus formed.

[0086] Gate electrodes 312 to 314 are defined by the above step (seeFIG. 3A). In the pixel matrix circuit, gate lines for connecting thegate electrodes are formed every other line at the same as the gateelectrodes are.

[0087] Thereafter, the gate insulating film 305 is etched by using thegate electrodes 312 to 314 as a mask by dry etching that uses a CF₄ gas.Gate insulating films 315 to 317 are thus formed so as to have shapesshown in FIG. 3B.

[0088] In this state, impurity ions for imparting one conductivity typeare added by ion implantation or plasma doping. P (phosphorus) ions maybe added if the pixel matrix circuit is to be constituted of n-type TFTsand B (boron) ions may added if it is to be constituted of p-type TFTs.

[0089] The above ion addition step is performed in two steps. In thefirst step, the acceleration voltage is set as high as about 80 kV sothat a peak of an impurity ion profile is located at the portions underthe end portions (projected portions) of the gate insulating films 315to 317. In the second step, the acceleration voltage is set as low asabout 5 kV so that so that impurity ions are not added to the portionsunder the end portions of the gate insulating films 315 to 317.

[0090] As a result, source regions 318 to 320, drain regions 321 to 323,low-concentration impurity regions (LDD regions) 324 to 326, and channelforming regions 327 to 329 of TFTs are formed (see FIG. 3B).

[0091] It is preferred that impurity ions be added to the source regions318 to 320 and the drain regions 321 to 323 so that a sheet resistanceof 300 to 500 Ω/□ is obtained there. It is necessary to optimize theimpurity concentration of the low-concentration impurity regions 324 to326 in accordance with the performance of the TFTs needed. Aftercompletion of the impurity ions addition step, a heat treatment isperformed to activate the impurity ions.

[0092] Then, a 400-nm-thick silicon oxide film is formed as a firstinterlayer insulating film 330, and source electrodes 331 to 333 anddrain electrodes 334 to 336 are formed therethrough (see FIG. 3C).

[0093] Thereafter, a silicon oxide film of 0.5 to 1 μm is formed as asecond interlayer insulating film 337. Forming a dense silicon oxidefilm by using a high-density plasma source, for instance, is preferredbecause the flatness attained by a later CMP step is improved. Thesecond interlayer insulting film 337 may be an organic resin film oncondition that the conditions of the CMP step is optimized. Examples ofmaterials of the organic resin film are polyimide, polyamide,polyimideamide, and acrylic.

[0094] After the formation of the second interlayer insulating film 337,a first CMP step is executed. The second interlayer insulating film 337is planarized by this step, whereby a flat surface without asperitiescan be obtained (see FIG. 3D).

[0095] Subsequently, a 100-nm-thick aluminum film containing titanium at1 wt % is formed and then patterned into pixel electrodes 338 to 340.Naturally other metal materials may be used.

[0096] Then, an insulating layer 341 is formed so as to cover the pixelelectrodes 338 to 340. Where the pixel electrodes are formed in such amanner that the boundary portions are located above the source lines 331to 333 as in the case of this embodiment, the source lines 331 to 333serve as a black mask. Therefore, the insulating layer 341 may betransparent.

[0097] However, to secure the light interrupting function more reliably,it is desirable that a light interruptive insulating film such as anorganic resin film in which a black pigment or carbon is dispersed (asolution-application-type silicon oxide film such as PSG) be used as theinsulating layer 341. With this measure, the light interrupting functioncan be attained reliably even in a case where the source lines 331 to333 are narrow or incident light comes obliquely.

[0098] By making the relative dielectric constant of the material of theinsulating layer 341 smaller than that of a liquid crystal used by aslarge a margin as possible, lateral electric fields developing betweenthe pixel electrodes 338 to 340 can be reduced.

[0099] The state of FIG. 4A is thus obtained. In this state, a secondCMP step is executed whereby buried insulating layers 342 to 344 areformed so as to be buried in the gaps between the pixel electrodes 338to 340. Since the surfaces of the pixel electrodes 338 to 340 areapproximately flush with the surfaces of the buried insulating layers342 to 344, a superior flat surface can be obtained (see FIG. 4B).

[0100]FIG. 6 is a simplified top view of the pixel matrix circuit inthis state. FIG. 4B is a sectional view taken along line A-A′ in FIG. 6.The reference numerals used in FIG. 6 are the same as in FIGS. 4A and4B.

[0101] As shown in FIG. 6, the pixel electrodes 338 to 340 etc. arearranged in matrix form and the gaps between those are buried by theburied insulating layers 342 to 344 etc. Therefore, although the buriedinsulating layers 342 to 344 are denoted by separate reference numerals,they are integral with each other and have a grid-like shape.

[0102] The pixel matrix circuit is completed in the above manner.Actually, driver circuits for driving the pixel TFTs and other circuitsare also formed on the same substrate at the same time. This type ofsubstrate is usually called a TFT-side substrate or an active matrixsubstrate. In this specification, this substrate is called a firstsubstrate.

[0103] After the completion of the first substrate, an opposed substrate(called a second substrate in this specification) in which an opposedelectrode 346 is formed on a transparent substrate 345 is bonded to thefirst substrate and a liquid crystal layer 347 is held between the firstand second substrates. A reflection-type LCD is thus completed as shownin FIG. 4C.

[0104] The above cell assembling may be performed according to a knownmethod. It is possible to disperse a dichroic dye in the liquid crystallayer 347 or provide color filters on the opposed substrate. The kind ofliquid crystal layer 347, the use of color filters, and other factorsmay be determined properly by a party who practices the inventionbecause they depend on the mode of driving the liquid crystal.

[0105] Embodiment 2

[0106] In this embodiment, an example process of manufacturing a pixelmatrix circuit of a transmission-type LCD by utilizing the first aspectof the invention will be described with reference to FIGS. 5A to 5C.Since the manufacturing process of this embodiment is the same as thatof the first embodiment to a certain intermediate step, only differentpoints between the two processes will be described below.

[0107] After the completion of the first CMP step shown in FIG. 3D,pixel electrodes 501 and 502 are formed as shown in FIG. 5A. In thisembodiment, the pixel electrodes 501 and 502 are transparent conductivefilms (made of ITO, SnO₂, or the like). The pixel electrodes 501 and 502are formed so as not to overlap with the TFTs.

[0108] Then, an insulating layer 503 is formed so as to cover the pixelelectrodes 501 and 502 (see FIG. 5A). In this embodiment, for example,polyimide in which a black pigment is dispersed is used as theinsulating layer 503. Since the active layers of the TFTs also need tobe shielded from light in the case of the transmission type, it ispreferred to use a light interruptive insulating film as the insulatinglayer 503.

[0109] Subsequently, a second CMP step is executed whereby buriedinsulating layers 504 and 505 are formed so as to be flush with thepixel electrodes 501 and 502 (see FIG. 5B).

[0110]FIG. 7 is a simplified top view of the pixel matrix circuit inthis state. FIG. 5B is a sectional view taken along line A-A′ in FIG. 7.The reference numerals used in FIG. 7 are the same as in FIGS. 5A and5B.

[0111] As shown in FIG. 7, the pixel electrodes 501, 502, etc. arearranged in matrix form and the gaps between those are filled in by theintegral buried insulating layers 504, 505, etc. In this embodiment, theburied insulating layers also formed over the TFTs provide an advantageof preventing a resistance variation that would otherwise be caused bylight incident on the active layers.

[0112] A TFT-side substrate of a transparent-type LCD is completed inthe above manner. After the completion of the TFT-side substrate, anordinary cell assembling step is executed whereby a liquid crystal layer508 is held between the TFT-side substrate and an opposed substrate thatis composed of a transparent substrate 506 and an opposed electrode 507.A transmission-type LCD is thus completed as shown in FIG. 5C.

[0113] In this embodiment, it is effective to planarize the pixelelectrodes 501 and 502 themselves by mechanically polishing those. Inthis case, it is preferable to provide a surface having minuteasperities for a direct-view display and a mirror surface for aprojection-type display.

[0114] Embodiment 3

[0115] Although in the manufacturing process of the first embodimentonly the second interlayer insulating film 337 and the insulating layer341 to be buried are planarized, in the invention the first interlayerinsulating film 330 may also be planarized.

[0116] Where an interlayer insulating film has a multilayered structure,a planarization step may be executed after formation of each constituentlayer.

[0117] In the invention, the flatness of the pixel electrode surfaces isimproved by securing a sufficient degree of flatness before formation ofpixel electrodes and then filling in the gaps between the pixelelectrodes by buried insulating layers. Therefore, the fact that thenumber of planarization steps is large causes no problem and is, rather,preferable.

[0118] Embodiment 4

[0119] This embodiment is directed to a case where TFTs having adifferent structure shown in the first embodiment are used assemiconductor elements for active matrix driving. The TFTs having thestructure of this embodiment can easily be applied to the secondembodiment.

[0120] Although the coplanar TFT, which is a typical example of thetop-gate TFT, is used in the first embodiment, the bottom-gate TFT maybe used. FIG. 8 shows a case where the inverted staggered structure TFT,which is a typical example of the bottom-gate TFT, is used.

[0121] In FIG. 8, reference numeral 801 denotes a glass substrate,numerals 802 and 803 denote gate electrodes, and numeral 804 denotes agate insulating film. Active layers 805 and 806 are silicon films thatare not intentionally doped with any impurity.

[0122] Reference numerals 807 and 808 denote source electrodes, numerals809 and 810 denote drain electrodes, and 811 and 812 denote siliconnitride films as channel stoppers (or etching stoppers). That is, theportions of the active layers 805 and 806 that are located under thechannel stoppers 811 and 812 substantially serve as channel formingregions, respectively.

[0123] The basic structure of the inverted staggered structure TFT hasbeen described above. In this embodiment, the inverted staggeredstructure TFTs are covered with an interlayer insulating film 813composed of an organic resin film, planarization is performed, and thenpixel electrodes 814 and 815 are formed. Naturally, the gaps between thepixel electrodes 814, 815, etc. are filled in by buried insulatinglayers 816 and 817 by utilizing the invention.

[0124] Next, a description will be made of a case where insulated-gatefield-effect transistors (IGFETs) are formed as semiconductor elementsof the invention. The IGFET, which is also called the MOSFET, is atransistor formed on a silicon wafer.

[0125] In FIG. 9, reference numeral 901 denotes a semiconductorsubstrate, numerals 902 and 903 denote source regions, and numerals 904and 905 denote drain regions. The source regions 902 and 903 and thedrain regions 904 and 905 can be formed by adding impurity ions by ionimplantation and then thermally diffusing those. A device isolationoxide layer 906 can be formed by an ordinary LOCOS technique.

[0126] Reference numeral 907 denotes a gate insulating film, numerals908 and 909 denote gate electrodes, a numeral 910 denotes a firstinterlayer insulating film, numerals 911 and 912 denote sourceelectrodes, and numerals 913 and 914 denote drain electrodes. A secondinterlayer insulating film 915 is formed, with planarization, on theabove components. Pixel electrodes 918 and 989 are formed on theplanarized surface of the second interlayer insulating film 915. Thegaps between the pixel electrodes 916, 917, etc. are filled in by buriedinsulating layers 918 and 919 by utilizing the invention.

[0127] In addition to the active matrix displays of this embodiment thatuse the IGFET or the top-gate or bottom-gate TFT, the first aspect ofthe invention can be applied to active matrix displays using thethin-film diode, the MIM element, the varistor element, or the like.

[0128] As described above in this embodiments, the first aspect of theinvention can be applied to reflection-type LCDs and transmission-typeLCDs using a semiconductor element of every structure.

[0129] In particular, in the case of the reflection-type LCD, the firstaspect of the invention provides an advantage that the area of eachpixel can be fully utilized by planarizing the structure above thesemiconductor element and forming a pixel electrode thereon. The firstaspect of the invention is effective in utilizing the that advantagemore effectively. Therefore, a reflection-type LCD manufactured byutilizing the invention can be given high resolution and a largeaperture ratio.

[0130] Embodiment 5

[0131] In this embodiment, an example process of manufacturing areflection-type LCD by utilizing the second aspect of the invention willbe described with reference to FIGS. 11A to 11D and 12A to 12C. Sincethe invention is directed to the technique relating to planarization ofpixels, the TFT structure itself is not limited to that in thisembodiment.

[0132] First, a substrate 1101 having an insulating surface is prepared.In this embodiment, a silicon oxide film as an undercoat film is formedon a glass substrate. Then, active layers 1102 to 1104 that arecrystalline silicon films are formed on the substrate 1101. Althoughonly three TFTs will be described in this embodiment, actually millionor more TFTs are formed in a pixel matrix circuit.

[0133] In this embodiment, a crystalline silicon film is obtained bythermally crystallizing an amorphous silicon film. The crystallinesilicon film is patterned into the active layers 1102 to 1104 by anordinary photolithography method. In this embodiment, a catalyst element(nickel) for accelerating crystallization is added in thecrystallization step. This technique is described in detail in JapaneseUnexamined Patent Publication No. Hei. 7-130652.

[0134] Then, a 150-nm-thick silicon oxide film is formed as a gateinsulating film 1105. An aluminum film (not shown) containing scandiumat 0.2 wt % is formed thereon and patterned into island-like patterns asstarting members of gate electrodes.

[0135] At this stage, in this embodiment, a technique disclosed inJapanese Unexamined Patent Publication No. Hei. 7-135318 is utilized.For details, refer to this publication.

[0136] First, anodization is performed in a 3%-aqueous solution ofoxalic acid in a state that the resist mask that was used in thepatterning is left on the island-like patterns. A platinum electrode isused as the cathode, the formation current is set at 2 to 3 mA, and thefinal voltage is set at 8 V. In this manner, porous anodic oxide films1106 to 1108 are formed.

[0137] After the resist mask is removed, anodization is again performedin a solution obtained by neutralizing 3%-ethylene glycol solution oftartaric acid with aqueous ammonia. The formation current and the finalvoltage may be set at 5 to 6 mA and 100 V, respectively. Dense anodicoxide films 1109 to 1111 are thus formed.

[0138] Gate electrodes 1112 to 1114 are defined by the above step (seeFIG. 11A). In the pixel matrix circuit, gate lines for connecting thegate electrodes are formed every other line at the same as the gateelectrodes are.

[0139] Thereafter, the gate insulating film 1105 is etched by using thegate electrodes 1112 to 1114 as a mask by dry etching that uses a CF⁴gas. Gate insulating films 1115 to 1117 are thus formed so as to haveshapes shown in FIG. 11B.

[0140] In this state, impurity ions for imparting one conductivity typeare added by ion implantation or plasma doping. P (phosphorus) ions maybe added if the pixel matrix circuit is to be constituted of n-type TFTsand B (boron) ions may added if it is to be constituted of p-type TFTs.

[0141] The above ion addition step is performed in two steps. In thefirst step, the acceleration voltage is set as high as about 80 kV sothat a peak of an impurity ion profile is located at the portions underthe end portions (projected portions) of the gate insulating films 1115to 1117. In the second step, the acceleration voltage is set as low asabout 5 kV so that impurity ions are not added to the portions under theend portions of the gate insulating films 1115 to 1117.

[0142] As a result, source regions 1118 to 1120, drain regions 1121 to1123, low-concentration impurity regions (LDD regions) 1124 to 1126, andchannel forming regions 1127 to 1129 of TFTs are formed (see FIG. 11B).

[0143] It is preferred that impurity ions be added to the source regions1118 to 1120 and the drain regions 1121 to 1123 so that a sheetresistance of 300 to 500 Ω/□ is obtained there. It is necessary tooptimize the impurity concentration of the low-concentration impurityregions 1124 to 1126 in accordance with the performance of the TFTsneeded. After completion of the impurity ions addition step, a heattreatment is performed to activate the impurity ions.

[0144] Then, a 400-nm-thick silicon oxide film is formed as a firstinterlayer insulating film 1130, and source electrodes 1131 to 1133 anddrain electrodes 1134 to 1136 are formed therethrough (see FIG. 11C).

[0145] Thereafter, a silicon oxide film of 0.5 to 1 μm is formed as asecond interlayer insulating film 1137. The second interlayer insultingfilm 1137 may be an organic resin film. Examples of materials of theorganic resin film are polyimide, polyamide, polyimideamide, acrylic andthe like.

[0146] After the formation of the second interlayer insulating film1137, a 100-nm-thick aluminum film containing titanium at 1 wt % isformed and then patterned into pixel electrodes 1138 to 1140. Naturallyother metal materials may be used.

[0147] Then, a DLC film 1141 is formed so as to cover the pixelelectrodes 1138 to 1140 by a vapor-phase method such as plasma CVD, ECRplasma CVD, sputtering, ion beam sputtering, or ionized evaporation.

[0148] Hydrocarbon is used as the material gas for forming the DLC film1141. Examples of usable hydrocarbons are saturated hydrocarbons such asmethane, ethane, and propane and unsaturated hydrocarbons such asethylene and acetylene. There may also be used halogenated hydrocarbonin which one or a plurality of hydrogen atoms of a hydrocarbon moleculeare replaced by halogen elements.

[0149] It is effective to add hydrogen to a hydrocarbon gas. Since theaddition of hydrogen increases hydrogen radicals in plasma, an effect ofremoving excess hydrogen atoms from the film and thereby improving thefilm quality is expected. It is preferable that the ratio of the flowrate of the hydrogen gas to that of the entire gas be 30 to 90% (50 to70% is even preferable). The film forming rate decreases if this ratiois too large, and the effect of removing excess hydrogen atoms is notobtained if it is too small.

[0150] Helium may be added as a carrier gas for diluting the materialgas. In the case of sputtering, argon may be added as a sputtering gas.As disclosed in Japanese Unexamined Patent Publication No. Hei.6-208721, it is effective to add an element of groups 13 to 15.

[0151] The reaction pressure may be set at 5 to 1,000 mTorr, preferably10 to 100 mTorr. The frequency of RF power is set at 13.56 MHz, which isusually employed, and the RF power is set at 0.01 to 1 W/cm², preferably0.05 to 0.5 W/cm². It is effective to add an excitation effect ofmicrowaves of 2.45 GHz to accelerate decomposition of the material gas.It is also effective to utilize electron spin resonance by forming amagnetic field of 875 Gauss in the microwave excitation space.

[0152] In this embodiment, a methane gas as a material gas and ahydrogen gas are introduced into the reaction space of a plasma CVDapparatus both at 50 sccm, and the film forming pressure is set at 10mTorr. The RF power is set at 100 W and the temperature of the reactionspace is set at the room temperature. Further, to increase the densityand the hardness of a resulting DLC film, a DC bias voltage of 200 V isapplied to the substrate to form an electric field that causes particles(ions) in the plasma to impinge on the film forming surface.

[0153] According to experiments of the inventors, forming a DLC film asthin as 10 nm can reduce the surface friction coefficient (center lineaverage roughness Ra) to 0.2 to 0.4, which is smaller than a practicalfriction coefficient 0.4. Further, almost no variation occurs infriction coefficient even if sliding action on the surface is repeated,which means that a DLC film as thin as 10 nm can sufficiently serve as astopper in a CMP step.

[0154] The friction coefficient depends on the thickness of the DLCfilm; it decreases as the thickness increases. From this viewpoint, thethickness of the DLC film 1141 may be 10 nm or more. However, if the DLCfilm 1141 is too thick, the electric field applied to the liquid crystalbecomes unduly weak. Therefore, the appropriate thickness range of theDLC film 1141 is about 10 to 50 nm.

[0155] In the case of the reflection-type LCD, a reflection enhancementtreatment which increases the reflectance by forming a dielectric on thesurface of the pixel electrodes is available. This utilizes thephenomenon that in general the reflectance of the pixel electrodesvaries depending on the thickness of the dielectric. The optimumthickness of the dielectric correlates with the wavelength of incidentlight. Therefore, in this embodiment, the reflectance can be increasedby optimizing the thickness of the DLC film 1141 in accordance withincident light.

[0156] For details of the film forming method, the film formingapparatus, etc., reference is made to Japanese Examined PatentPublication Nos. Hei. 3-72711, Hei. 4-27690, and Hei. 4-27691 of thepresent inventors.

[0157] After the DLC film 1141 is formed in the above manner, aninsulating layer 1142 for filling in the boundary portions (gaps)between the pixel electrodes 1138 to 1140. Where the pixel electrodesare formed in such a manner that the boundary portions are located abovethe source lines 1131 to 1133 as in the case of this embodiment, thesource lines 1131 to 1133 serve as a black mask. Therefore, theinsulating layer 1142 may be transparent.

[0158] However, to secure the light interrupting function more reliably,it is desirable that a light interruptive insulating film such as anorganic resin film in which a black pigment or carbon is dispersed (asolution-application-type silicon oxide film such as PSG) be used as theinsulating layer 1142. With this measure, the light interruptingfunction can be attained reliably even in a case where the source lines1131 to 1133 are narrow or incident light comes obliquely.

[0159] By making the relative dielectric constant of the material of theinsulating layer 1142 than that of a liquid crystal used by as large amargin as possible, lateral electric fields developing between the pixelelectrodes 1138 to 1140 can be reduced.

[0160] The state of FIG. 12A is thus obtained. In this state, a CMP stepfor planarizing the insulating layer 1142 is executed whereby buriedinsulating layers 1143 to 1145 are formed so as to be buried in the gapsbetween the pixel electrodes 1138 to 1140 (see FIG. 12B).

[0161] Since the surfaces of the pixel electrodes 1138 to 1140 areapproximately flush with the surfaces of the buried insulating layers1143 to 1145, a superior flat surface can be obtained. Further, sincethe surfaces of the pixel electrodes 1138 to 1140 are protected by theDLC film 1141, excessive polishing can be prevented.

[0162]FIG. 14 is a simplified top view of the pixel matrix circuit inthis state. FIG. 12B is a sectional view taken along line A-A′ in FIG.14. The reference numerals used in FIG. 14 are the same as in FIGS. 12Aand 12B.

[0163] As shown in FIG. 14, the pixel electrodes 1138 to 1140 etc. arearranged in matrix form and their surfaces are covered with the DLC film1141. The gaps between the pixel electrodes 1138 to 1140 etc. are buriedby the buried insulating layers 1143 to 1145 etc. Therefore, althoughthe buried insulating layers 1143 to 1145 are denoted by separatereference numerals, they are integral with each other and have agrid-like shape.

[0164] The pixel matrix circuit is completed in the above manner.Actually, driver circuits for driving the pixel TFTs and other circuitsare also formed on the same substrate at the same time. This type ofsubstrate is usually called a TFT-side substrate or an active matrixsubstrate. In this specification, this substrate is called a firstsubstrate.

[0165] After the completion of the first substrate, an opposed substrate(called a second substrate in this specification) in which an opposedelectrode 1147 is formed on a transparent substrate 1146 is bonded tothe first substrate and a liquid crystal layer 1148 is held between thefirst and second substrates. A reflection-type LCD is thus completed asshown in FIG. 12C.

[0166] The above cell assembling may be performed according to a knownmethod. It is possible to disperse a dichroic dye in the liquid crystallayer 1148 or provide color filters on the opposed substrate. The kindof liquid crystal layer 1148, the use of color filters, and otherfactors may be determined properly by a party who practices theinvention because they depend on the mode of driving the liquid crystal.

[0167] Embodiment 6

[0168] In this embodiment, an example process of manufacturing a pixelmatrix circuit of a transmission-type LCD by utilizing the second aspectof the invention will be described with reference to FIGS. 13A to 13C.Since the manufacturing process of this embodiment is the same as thatof the fifth embodiment to a certain intermediate step, only differentpoints between the two processes will be described below.

[0169]FIG. 13A shows a state that pixel electrodes 1301 and 1302, a DLCfilm 1303, and an insulating layer 1304 to be buried have been formed bythe same steps as in the fifth embodiment. In this embodiment, the pixelelectrodes 1301 and 1302 are transparent conductive films (made of ITO,SnO₂, or the like). The pixel electrodes 1301 and 1302 are formed so asnot to overlap with the TFTs.

[0170] In this embodiment, for example, polyimide in which a blackpigment is dispersed is used as the insulating layer 1304. Since theactive layers of the TFTs also need to be shielded from light in thecase of the transmission type, it is preferred to use a lightinterruptive insulating film as the insulating layer 1304.

[0171] Subsequently, a CMP step is executed whereby buried insulatinglayers 1305 and 1306 are formed so as to be flush with the pixelelectrodes 1301 and 1302 (more correctly, with the DLC film 1303; seeFIG. 13B).

[0172]FIG. 15 is a simplified top view of the pixel matrix circuit inthis state. FIG. 13B is a sectional view taken along line B-B′ in FIG.15. The reference numerals used in FIG. 15 are the same as in FIGS. 13Aand 13B.

[0173] As shown in FIG. 15, the pixel electrodes 1301, 1302, etc. arearranged in matrix form and their surfaces are covered with the DLC film1303. The gaps between the pixel electrodes 1301, 1302, etc. are filledin by the integral buried insulating layers 1305, 1306, etc. In thisembodiment, the buried insulating layers 1305, 1306 also formed over theTFTs provide an advantage of preventing a resistance variation thatwould otherwise be caused by light incident on the active layers.

[0174] A TFT-side substrate is completed in the above manner. After thecompletion of the TFT-side substrate, an ordinary cell assembling stepis executed whereby a liquid crystal layer 1309 is held between theTFT-side substrate and an opposed substrate that is composed of atransparent substrate 1307 and an opposed electrode 1308. Atransmission-type LCD is thus completed as shown in FIG. 13C.

[0175] Embodiment 7

[0176] In the fifth embodiment, it is effective to planarize the pixelelectrodes 1138 to 1140 before the formation of the DLC film 1141. It ispreferable that this planarization step be a CMP step.

[0177] In the second aspect of the invention, since the DLC film is usedas a stopper film in the mechanical polishing step, the surface state ofthe DLC film reflects the surface state itself of the pixel electrodes.Therefore, where the surfaces of the pixel electrodes are required to behighly flat as in the case of the reflection-type LCD, the surfaces ofthe pixel electrodes should be made highly flat in advance.

[0178] Embodiment 8

[0179] This embodiment is directed to a case where TFTs having adifferent structure than in the fifth embodiment are used assemiconductor elements for active matrix driving. The TFTs having thestructure of this embodiment can easily be applied to the sixthembodiment.

[0180] Although the coplanar TFT, which is a typical example of thetop-gate TFT, is used in the fifth embodiment, the bottom-gate TFT maybe used. FIG. 16 shows a case where the inverted staggered structureTFT, which is a typical example of the bottom-gate TFT, is used.

[0181] In FIG. 16, reference numeral 1601 denotes a glass substrate,numerals 1602 and 1603 denote gate electrodes, and numeral 1604 denotesa gate insulating film. Active layers 1605 and 1606 are silicon filmsthat are intentionally not doped with any impurity.

[0182] Reference numerals 1607 and 1608 denote source electrodes,numerals 1609 and 1610 denote drain electrodes, and 1611 and 1612 denotesilicon nitride films as channel stoppers (or etching stoppers). Thatis, the portions of the active layers 1605 and 1606 that are locatedunder the channel stoppers 1611 and 1612 substantially serve as channelforming regions, respectively.

[0183] The basic structure of the inverted staggered structure TFT hasbeen described above. In this embodiment, the inverted staggeredstructure TFTs are covered with an interlayer insulating film 1613composed of an organic resin film, planarization is performed, and thenpixel electrodes 1614 and 1615 are formed. In a state that the pixelelectrodes 1614 and 1615 are protected by the DLC film 1616, aninsulating layer to be buried is formed and then planarized by a CMPstep. The gaps between the pixel electrodes 1614, 1615, etc. are filledin by buried insulating layers 1617 and 1618.

[0184] Next, a description will be made of a case where insulated-gatefield-effect transistors (IGFETs) are formed as semiconductor elementsof the invention. The IGFET, which is also called the MOSFET, is atransistor formed on a silicon wafer.

[0185] In FIG. 17, reference numeral 1701 denotes a semiconductorsubstrate, numerals 1702 and 1703 denote source regions, and numerals1704 and 1705 denote drain regions. The source regions 1702 and 1703 andthe drain regions 1704 and 1705 can be formed by adding impurity ions byion implantation and then thermally diffusing those. A device isolationoxide layer 1706 can be formed by an ordinary LOCOS technique.

[0186] Reference numeral 1707 denotes a gate insulating film, numerals1708 and 1709 denote gate electrodes, a numeral 1710 denotes a firstinterlayer insulating film, numerals 1711 and 1712 denote sourceelectrodes, and numerals 1713 and 1714 denote drain electrodes. A secondinterlayer insulating film 1715 is formed on the above components andpixel electrodes 1716 and 1717 are formed on the second interlayerinsulating film 1715. Also in this case, the pixel electrodes 1716 and1717 are protected by the DLC film 1718 and the boundary portions arefilled in by buried insulating layers 1719 and 1720.

[0187] In addition to the active matrix displays of this embodiment thatuse the IGFET or the top-gate or bottom-gate TFT, the second aspect ofthe invention can be applied to active matrix displays using thethin-film diode, the MIM element, the varistor element, or the like.

[0188] As described above in this embodiments, the second aspect of theinvention can be applied to reflection-type LCDs and transmission-typeLCDs using a semiconductor element of every structure.

[0189] In particular, in the case of the reflection-type LCD, the secondaspect of the invention provides an advantage that the area of eachpixel can be fully utilized by planarizing the structure above thesemiconductor element and forming a pixel electrode thereon. The secondaspect of the invention is effective in utilizing such advantage moreeffectively. Therefore, a reflection-type LCD manufactured by utilizingthe second aspect of the invention can be given high resolution and alarge aperture ratio.

[0190] Embodiment 9

[0191] In the fifth embodiment, it is effective to planarize the secondinterlayer insulating film 1137 before forming the pixel electrodes 1138to 1140.

[0192] There are various methods suitable for planarizing an interlayerinsulating film, such as a method of forming an inter layer insulatingfilm thicker than a necessary thickness, a leveling method using anorganic resin film, a mechanical polishing method, and a method using ametch back technique. Among those methods, the mechanical polishingmethod is most effective in obtaining a superior flat surface.

[0193] A typical example of the mechanical polishing method is a CMP(chemical mechanical polishing technique. The CMP technique is apolishing technique that is a combination of chemical etching with aliquid chemical and mechanical polishing with an abrasive.

[0194] According to this embodiment, since the pixel electrodes 1138 to1140 are formed on a superior flat surface, they are given a highreflectance. Therefore, this embodiment is very effective when appliedto projection-type displays or like uses.

[0195] Embodiment 10

[0196] The invention can also be applied to a passive matrix liquidcrystal display device. In this case, striped electrodes are formed oneach of two substrates, the two substrates are bonded together so thatthe striped electrodes are rendered perpendicular to each other, and aliquid crystal layer is held between the two substrates.

[0197] In this case, if one substrate is transparent, the other may beeither transparent or light interruptive. However, the stripedelectrodes formed on the transparent substrate should be transparentconductive films.

[0198] In this embodiment, striped electrodes made only or mainly ofaluminum are formed on the substrate that is opposed to the transparentsubstrate and the gaps between the striped electrodes are filled in byinsulating layers.

[0199] Where the invention is applied to a passive matrix LCD, anadvantage of a reduction in crosstalk between adjacent electrodes can beobtained by forming the insulating layers by using a material (forinstance, an organic resin material) having a smaller relativedielectric constant than the liquid crystal layer.

[0200] Embodiment 11

[0201] Reflection-type LCDs manufactured by utilizing the invention mayemploy various kinds of liquid crystal display modes such as the ECB(electric-field-controlled birefringence) mode, the PCGH (phase changeguest-host)mode, the OCB mode, the HAN mode, and the PDLC-typeguest-host mode.

[0202] The ECB mode is a display mode in which the liquid crystalalignment is varied by changing the voltage applied to the liquidcrystal layer and a resulting variation in birefringence of the liquidcrystal layer is detected by a pair of polarizing plates. Color displayis performed in this mode. This mode enables a scheme that does not usecolor filters, in which case bright display is possible.

[0203] The PCGH mode is a display mode in which a dichroic dye as guestmolecules is mixed into a host liquid crystal and the light absorptioncoefficient of the liquid crystal layer is varied by changing thealignment state of liquid crystal molecules by the voltage applied tothe liquid crystal layer. This mode enables a scheme that uses nopolarizing plates, in which case high contrast can be obtained.

[0204] The PDLC mode is a display mode which uses a polymer dispersionliquid crystal in which a polymer is dispersed in a liquid crystal (orvice versa). Because no polarizing plates are needed, this mode enablesbright display. Further, by using a solid-state polymer dispersionliquid crystal, a configuration without a glass substrate on theopposing side can be realized.

[0205] In each of the above-mentioned various kinds of display modes,whether to use polarizing plates or color filters can be determinedfreely in accordance with the features of the display mode. For example,in the case of the PCGH mode, bright display can be attained even by asingle plate configuration using color filters because no polarizingplates are needed.

[0206] Embodiment 12

[0207] This embodiment is directed to examples of electro-opticaldevices in which the invention is applied to a display device. First, athree-plate projector using reflection-type LCDs according to the firstor fifth embodiment will be described with reference to FIG. 19A.

[0208] As shown in FIG. 19A, light including R (red), B (blue), and G(green) components that is output from a light source 11 such as a metalhalide lamp or a halogen lamp is reflected by a polarizing beam splitter12 so as to proceed to a crossed dichroic mirror 13.

[0209] The polarizing beam splitter is an optical filter having afunction of reflecting or transmitting light depending on itspolarization direction. In this embodiment, the light emitted from thelight source 11 is given such polarization that the light is reflectedby the polarizing beam splitter 12.

[0210] The crossed dichroic mirror 13 reflects the R-component light andthe B-component light toward an R liquid crystal panel 14 and a B liquidcrystal panel 15, respectively. The G-component light passes through thecrossed dichroic mirror 13 and enters a G liquid crystal panel 16.

[0211] In each of the liquid crystal panels 14 to 16, liquid crystalmolecules are aligned so that the liquid crystal panel reflects incidentlight without changing its polarization direction if a pixel is in anoff state. If a pixel is in an on state, the alignment direction ofliquid crystal molecules is changed and accordingly incident light issubjected to a change in polarization direction.

[0212] After being reflected by the respective liquid crystal panels 14to 16, the component beams are combined together in again beingreflected by (R and B) or passing through (G) the crossed dichroicmirror 13. The combined light again enters the polarizing beam splitter12.

[0213] At this time, light that was reflected by an on-state pixelregion was changed in polarization direction and hence passes throughthe polarizing beam splitter 12. On the other hand, light that wasreflected by an off-state pixel region was not changed in polarizationdirection and hence is reflected by the polarizing beam splitter 12.

[0214] As described above, by on/off-controlling pixel regions that arearranged in matrix form in the pixel matrix circuit with a number ofsemiconductor elements, only light beams that are reflected byparticular pixel regions are allowed to pass through the polarizing beamsplitter 12. This operation is common to the liquid crystal panels 14 to16.

[0215] The light containing image information that has passed throughthe polarizing beam splitter 12 in the above manner is enlarged andprojected onto a screen 18 by an optical lens 17 such as a projectionlens.

[0216] Since the gaps between the pixel electrodes are filled in, areflection-type LCD according to the invention is given high resolutionand a high aperture ratio. Where the pixel electrodes are furthersubjected to planarization, the reflection-type LCD has a highreflectance. Therefore, the reflection type LCD can attain superiordisplay performance even when used in electro-optical devices thatprojects an image in an enlarged manner as in the case of the projectorshown in FIG. 19A.

[0217] Next, with reference to FIG. 19B, a description will be made of athree-plate projector which uses transmission-type LCDs according to thesecond or sixth embodiment.

[0218] In FIG. 19B, reference numerals 19 and 20 denote a light sourcesuch as a halogen lamp and a reflector, respectively. Light containingR, G, and B components enters a dichroic mirror 21 and only theR-component light is reflected by the same. The R-component light isthen reflected by a reflector 22 and enters an R liquid crystal panel23.

[0219] Light that has passed through the dichroic mirror 21 enters adichroic mirror 24 and only B-component light is reflected by the same.The B-component light then enters a B liquid crystal panel 25.G-component light that has passed through the dichroic mirror 24 entersa G liquid crystal panel 26.

[0220] The R-component light is combined with the B-component light by adichroic mirror 27 and resulting light enters a dichroic mirror 28. TheG-component light is reflected by a reflector 29 and enters a dichroicmirror 28, where all the R, G, and B component beams are combinedtogether. Resulting light is enlarged and projected onto a screen 31 bya projection lens 30.

[0221] Having high resolution and a high aperture ratio, thetransmission-type LCD according to the invention can realizeelectro-optical devices having superior display performance. Inparticular, the high aperture ratio is the most significant advantage ofthe transmission-type LCD according to the invention.

[0222] Embodiment 13

[0223] In this embodiment, application projects (electro-opticaldevices) to which a liquid crystal display device of the invention canbe applied will be described with reference to FIGS. 20A to 20F.Examples of electro-optical devices utilizing the invention are a videocamera, a still camera, a projector, a head-mounted display, a carnavigation apparatus, a personal computer, and a portable informationterminal (a mobile computer, a cellular telephone, etc.).

[0224]FIG. 20A shows a mobile computer, which consists of a main body2001, a camera section 2002, an image receiving section 2003, amanipulation switch 2004, and a display device 2005. The mobile computercan further be miniaturized and reduced in power consumption by using areflection-type LCD of the invention in the display device 2005.

[0225]FIG. 20B shows a head-mounted display, which consists of a mainbody 2101, display devices 2102, and a band section 2103. Thehead-mounted display can greatly be miniaturized by using areflection-type LCD of the invention in the display devices 2102.

[0226]FIG. 20C shows a front projector, which consists of a main body2201, a light source 2202, a display device 2203, am optical system2204, and a screen 2205. A high-resolution image can be realized byusing a transmission-type LCD of the invention in the display device2203.

[0227]FIG. 20D shows a cellular telephone, which consists of a main body2301, a voice output section 2302, a voice input section 2303, a displaydevice 2304, manipulation switches 2305, and an antenna 2306. Byapplying the invention to the display device 2304, the cellulartelephone can be mounted with a display monitor that is superior invisibility.

[0228]FIG. 20E shows a video camera, which consists of a main body 2401,a display device 2402, a sound input section 2403, manipulation switches2404, a battery 2405, and an image receiving section 2406. By applyingthe invention to the display device 2402, superior display performancethat enables outdoor photographing well can be obtained.

[0229]FIG. 20F shows a rear projector, which consists of a main body2501, a light source 2502, a display device 2503, a polarizing beamsplitter 2504, reflectors 2505 and 2506, and a screen 2507. The rearprojector can be thinned and a high-resolution image can be realized byusing a reflection-type LCD of the invention in the display device 2503.

[0230] In the case of the direct-view displays (see FIGS. 20A, 20B, 20D,and 20E), it is effective to form asperities on the pixel electrodesurfaces because the asperities enhance the light scattering effect andthereby increase the view field angle and improve the visibility. In thecase of the projection-type displays (see FIGS. 20C and 20F), it ispreferred that the pixel electrode surfaces be mirror surfaces. Thisreduces diffused reflection of light, thereby preventing a colordeviation or a reduction in resolution.

[0231] As described above, the application range of the invention isextremely wide and the invention can be applied to display media ofevery field. Where a liquid crystal display device is used inprojection-type display devices such as a projector, it is required tohave high resolution. The invention is particularly effective for such acase.

[0232] Portable information terminal equipment (personal digitalassistants) that is typified by a mobile computer, a portable telephone,and a video camera is desired to be compact and low in powerconsumption. A reflection-type LCD that does not require a backlight iseffective for such a case.

[0233] In a liquid crystal display device utilizing the invention, thegaps between the pixel electrodes that are arranged in matrix form arefilled in by buried insulating layers. As a result, the surfaces of thepixel electrodes are approximately flush with those of the buriedinsulating layers; that is, the step portions at the gaps between thepixel electrodes are planarized almost completely.

[0234] Therefore, the problems resulting from the step portions, such asalignment failures of a liquid crystal material and a contrast reductiondue to diffused reflection of incident light, can be solved. Since theinterlayer insulating film as an undercoat of the pixel electrodes isplanarized in advance, the pixel electrodes are rendered completelyflat.

[0235] As a result, a liquid crystal display device having a highaperture ratio and a high reflectance and exhibiting high-resolutiondisplay performance can be realized.

[0236] The buried insulating layers are obtained by planarizing aninsulating layer that has been formed so as to be thicker than anecessary thickness. In particular, where the insulating layer isplanarized by a mechanical polishing step (CMP step), excessivepolishing of the pixel electrodes can be prevented by forming a DLC filmbetween the pixel electrodes and the insulting film.

[0237] That is, since the CMP step is substantially finished at the timepoint when the DLC film is exposed, the control of the processing timecan greatly be simplified. This is very effective in increasing theproduction yield.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising the steps of: planarizing an insulating film formed over asubstrate having an insulating surface; forming a plurality ofelectrodes on the insulating film; forming an insulating layer so as tocover the plurality of electrodes; and planarizing surfaces of theplurality of electrodes and a surface of the insulating layer so thatthey become flush with each other, thereby filling boundary portionsbetween the plurality of electrodes with the insulating layer.
 2. Amethod according to claim 1 , wherein mechanical polishing is performedin each of the planarizing steps.
 3. A method according to claim 1 ,wherein the insulating layer is light interruptive.
 4. A methodaccording to claim 1 , wherein the insulating layer is an organic resinfilm in which a black pigment or a carbon-type material is dispersed. 5.A method of manufacturing a semiconductor device comprising the stepsof: planarizing an insulating film formed over a first substrate;forming striped electrodes on the insulating film; forming an insulatinglayer so as to cover the striped electrodes; and planarizing surfaces ofthe striped electrodes and a surface of the insulating layer so thatthey become flush with each other, thereby filling boundary portionsbetween the striped electrodes with the insulating layer; and forming aliquid crystal layer between the first substrate and a secondtransparent substrate.
 6. A method according to claim 5 , whereinmechanical polishing is performed in each of the planarizing steps.
 7. Amethod according to claim 5 , wherein the insulating layer is lightinterruptive.
 8. A method according to claim 5 , wherein the insulatinglayer is an organic resin film in which a black pigment or a carbon-typematerial is dispersed.
 9. A method of manufacturing a semiconductordevice, comprising the steps of: forming a plurality of semiconductorelements over a substrate having an insulating surface; forming aninterlayer insulating film over the semiconductor elements; planarizingthe interlayer insulating film; forming pixel electrodes that areelectrically connected to the respective semiconductor elements on theinterlayer insulating film; forming an insulating layer so as to coverthe pixel electrodes; and planarizing surfaces of the pixel electrodesand a surface of the insulating layer so that they become flush witheach other, thereby filling boundary portions between the pixelelectrodes with the insulating layer.
 10. A method according to claim 9, wherein mechanical polishing is performed in each of the planarizingsteps.
 11. A method according to claim 9 , wherein the insulating layeris light interruptive.
 12. A method according to claim 9 , wherein theinsulating layer is an organic resin film in which a black pigment or acarbon-type material is dispersed.
 13. A method according to claim 9 ,wherein the semiconductor elements are thin-film transistors.
 14. Amethod of manufacturing a semiconductor device, comprising the steps of:forming a plurality of semiconductor elements arranged in matrix formover a first substrate; forming an interlayer insulating film over thesemiconductor elements; planarizing the interlayer insulating film;forming a plurality of pixel electrodes that are electrically connectedto the respective semiconductor elements on the interlayer insulatingfilm; forming an insulating layer so as to cover the pixel electrodes;planarizing surfaces of the pixel electrodes and a surface of theinsulating layer so that they become flush with each other, therebyfilling boundary portions between the pixel electrodes with theinsulating layer; and forming a liquid crystal layer between the firstsubstrate and a second transparent substrate.
 15. A method according toclaim 14 , wherein mechanical polishing is performed in each of theplanarizing steps.
 16. A method according to claim 14 , wherein theinsulating layer is light interruptive.
 17. A method according to claim14 , wherein the insulating layer is an organic resin film in which ablack pigment or a carbon-type material is dispersed.
 18. A method ofmanufacturing a semiconductor device, comprising the steps of: forming aplurality of electrodes over a substrate having an insulating surface;forming a DLC film to cover the plurality of electrodes; forming aninsulating layer on the DLC film; and planarizing the insulating layerso that a surface of the DLC film and a surface of the insulating layerbecome flush with each other, thereby filling boundary portions of theplurality of electrodes with the insulating layer.
 19. A methodaccording to claim 18 , wherein mechanical polishing is performed in theplanarizing step.
 20. A method according to claim 18 , furthercomprising, before the step of forming the DLC film, the step ofplanarizing the plurality of electrodes.
 21. A method according to claim18 , wherein the insulating layer is light interruptive.
 22. A methodaccording to claim 18 , wherein the insulating layer is an organic resinfilm in which a black pigment or a carbon-type material is dispersed.23. A method of manufacturing a semiconductor device, comprising thesteps of: forming striped electrodes over a first substrate; forming aDLC film to cover the striped electrodes; forming an insulating layer onthe DLC film; planarizing the insulating layer so that a surface of theDLC film and a surface of the insulating layer become flush with eachother, thereby filling boundary portions of the striped electrodes withthe insulating layer; and forming a liquid crystal layer between thefirst substrate and a second transparent substrate.
 24. A methodaccording to claim 23 , wherein mechanical polishing is performed in theplanarizing step.
 25. A method according to claim 23 , furthercomprising, before the step of forming the DLC film, the step ofplanarizing the striped electrodes.
 26. A method according to claim 23 ,wherein the insulating layer is light interruptive.
 27. A methodaccording to claim 23 , wherein the insulating layer is an organic resinfilm in which a black pigment or a carbon-type material is dispersed.28. A method according to claim 23 , wherein the DLC film has athickness in a range of 10 to 50 nm.
 29. A method of manufacturing asemiconductor device, comprising the steps of: forming a plurality ofsemiconductor elements over a substrate having an insulating surface;forming a plurality of pixel electrodes that are electrically connectedto the respective semiconductor elements; forming a DLC film to coverthe pixel electrodes; forming an insulating layer on the DLC film; andplanarizing the insulating layer so that a surface of the DLC film and asurface of the insulating layer become flush with each other, therebyfilling boundary portions of the pixel electrodes with the insulatinglayer.
 30. A method according to claim 29 , wherein mechanical polishingis performed in the planarizing step.
 31. A method according to claim 29, further comprising, before the step of forming the DLC film, the stepof planarizing the pixel electrodes.
 32. A method according to claim 29, wherein the semiconductor elements are thin-film transistors.
 33. Amethod according to claim 29 , wherein the insulating layer is lightinterruptive.
 34. A method according to claim 29 , wherein theinsulating layer is an organic resin film in which a black pigment or acarbon-type material is dispersed.
 35. A method of manufacturing asemiconductor device comprising the steps of: forming a plurality ofsemiconductor elements arranged in matrix form over a substrate; forminga plurality of pixel electrodes connected to the respectivesemiconductor elements, with at least one interlayer insulating filminterposed therebetween; forming a DLC film to cover the pixelelectrodes; forming an insulating layer on the DLC film; and planarizingthe insulating layer so that a surface of the DLC film and a surface ofthe insulating layer become flush with each other, thereby fillingboundary portions of the plurality of the pixel electrodes with theinsulating layer; and forming a liquid crystal layer over the planarizedinsulating layer.
 36. A method according to claim 35 , whereinmechanical polishing is performed in the planarizing step.
 37. A methodaccording to claim 35 , further comprising, before the step of formingthe DLC film, the step of planarizing the pixel electrodes.
 38. A methodaccording to claim 35 , wherein the insulating layer is lightinterruptive.
 39. A method according to claim 35 , wherein theinsulating layer is an organic resin film in which a black pigment or acarbon-type material is dispersed.
 40. A semiconductor devicecomprising: an insulating surface formed over a substrate; a pluralityof electrodes formed over said insulating surface; and a DLC filmcovering the plurality of electrodes and portions of said insulatingsurface, wherein the DLC film has a thickness in a range of 10 to 50 nm.41. A device according to claim 40 , wherein each of said portions ofthe insulating surface is exposed in a gap between two adjacentelectrodes.
 42. A device according to claim 40 , further comprising aninsulating layer formed over said portions of said insulating surfacewith said DLC film interposed therebetween so as to be buried in gapsbetween the plurality of electrodes.
 43. A device according to claim 42, wherein the insulating layer is light interruptive.
 44. A deviceaccording to claim 42 , wherein the insulating layer is an organic resinfilm in which a black pigment or a carbon-type material is dispersed.45. A device according to claim 42 , wherein exposed surfaces of saidDLC film are approximately flush with surfaces of the buried insulatinglayer.
 46. A device according to claim 40 , wherein said electrodes areconnected with a plurality of semiconductor elements formed in matrixform over said insulating surface.
 47. A device according to claim 46 ,wherein the semiconductor elements are selected from the groupconsisting of top gate thin-film transistors, bottom gate thin-filmtransistors, insulated gate field effect transistors (IGFETs), thin-filmdiodes, MIM (metal-insulator-metal) elements, and varistor elements. 48.A device according to claim 40 , wherein said semiconductor device is anelectro-optical device selected from the group consisting of a videocamera, a still camera, a projector, a head-mounted display, a carnavigation apparatus, a personal computer, a portable informationterminal, a mobile computer, and a cellular telephone.
 49. Asemiconductor device comprising: an insulating surface formed over asubstrate; a plurality of electrodes formed over said insulatingsurface; and a DLC film covering the plurality of electrodes andportions of said insulating surface, wherein said DLC film has a Vickershardness of 2,000 kg/mm² or more and a friction coefficient of 0.4 orless.
 50. A device according to claim 49 , wherein each of said portionsof the insulating surface is exposed in a gap between two adjacentelectrodes.
 51. A device according to claim 49 , further comprising aninsulating layer formed over said portions of said insulating surfacewith said DLC film interposed therebetween so as to be buried in gapsbetween the plurality of electrodes.
 52. A device according to claim 51, wherein the insulating layer is light interruptive.
 53. A deviceaccording to claim 51 , wherein the insulating layer is an organic resinfilm in which a black pigment or a carbon-type material is dispersed.54. A device according to claim 51 , wherein exposed surfaces of saidDLC film are approximately flush with surfaces of the buried insulatinglayer.
 55. A device according to claim 18 , wherein said electrodes areconnected with a plurality of semiconductor elements formed in matrixform over said insulating surface.
 56. A device according to claim 55 ,wherein the semiconductor elements are selected from the groupconsisting of top gate thin-film transistors, bottom gate thin-filmtransistors, insulated gate field effect transistors (IGFETs), thin-filmdiodes, MIM (metal-insulator-metal) elements, and varistor elements. 57.A device according to claim 49 , wherein said semiconductor device is anelectro-optical device selected from the group consisting of a videocamera, a still camera, a projector, a head-mounted display, a carnavigation apparatus, a personal computer, a portable informationterminal, a mobile computer, and a cellular telephone.
 58. Asemiconductor device comprising: a substrate; a plurality of switchingelements arranged in matrix form; an interlayer insulating film formedover said switching elements; a plurality of pixel electrodes formedover said interlayer insulating film and connected to said switchingelements, respectively; and a protection film covering said pixelelectrodes and portions of said interlayer insulating film, wherein saidprotection film has a thickness in a range of 10 to 50 nm.
 59. A deviceaccording to claim 58 , further comprising buried insulating layersformed over said portions with said protection film interposedtherebetween for filling gaps between said pixel electrodes.
 60. Adevice according to claim 59 , wherein exposed surfaces of saidprotection film are approximately flush with surfaces of the buriedinsulating layers.
 61. A device according to claim 59 , wherein saidburied insulating layers comprise an organic resin in which a blackpigment or a carbon-type material is dispersed.
 62. A device accordingto claim 59 wherein a hardness of said protection film is higher thanthose of buried insulating layers.
 63. A device according to claim 58 ,wherein each of said switching elements is selected from the groupconsisting of a top gate thin-film transistor, a bottom gate thin-filmtransistor, an insulated gate field effect transistor (IGFET), athin-film diode, an MIM (metal-insulator-metal) element, and a varistorelement.
 64. A device according to claim 58 , wherein said interlayerinsulating film comprises a material selected from the group consistingof silicon oxide, polyimide, polyamide, polyimideamide, and acrylic. 65.A device according to claim 58 , wherein said protection film comprisesdiamond-like carbon.
 66. A device according to claim 58 , wherein saidsemiconductor device is an electro-optical device selected from thegroup consisting of a video camera, a still camera, a projector, ahead-mounted display, a car navigation apparatus, a personal computer, aportable information terminal, a mobile computer, and a cellulartelephone.
 67. A device according to claim 58 , wherein each of saidportions of the interlayer insulating film is exposed in a gap betweentwo adjacent pixel electrodes.
 68. A semiconductor device comprising: asubstrate; a plurality of switching elements arranged in matrix form; aninterlayer insulating film formed over said switching elements; aplurality of pixel electrodes formed over said interlayer insulatingfilm and connected to said switching elements, respectively; and aprotection film covering said pixel electrodes and portions of saidinterlayer insulating film, said protection film has a Vickers hardnessof 2,000 kg/mm² or more and a friction coefficient of 0.4 or less.
 69. Adevice according to claim 68 , further comprising buried insulatinglayers formed over said portions with said protection film interposedtherebetween for filling gaps between said pixel electrodes.
 70. Adevice according to claim 69 wherein exposed surfaces of said protectionfilm are approximately flush with surfaces of the buried insulatinglayers.
 71. A device according to claim 69 , wherein said buriedinsulating layers comprise an organic resin in which a black pigment ora carbon-type material is dispersed.
 72. A device according to claim 69, wherein a hardness of said protection film is higher than those ofburied insulating layers.
 73. A device according to claim 68 , whereineach of said switching elements is selected from the group consisting ofa top gate thin-film transistor, a bottom gate thin-film transistor, aninsulated gate field effect transistor (IGFET), a thin-film diode, anMIM (metal-insulator-metal) element, and a varistor element.
 74. Adevice according to claim 68 , wherein said interlayer insulating filmcomprises a material selected from the group consisting of siliconoxide, polyimide, polyamide, polyimideamide, and acrylic.
 75. A deviceaccording to claim 68 , wherein said protection film comprisesdiamond-like carbon.
 76. A device according to claim 68 , wherein saidsemiconductor device is an electro-optical device selected from thegroup consisting of a video camera, a still camera, a projector, ahead-mounted display, a car navigation apparatus, a personal computer, aportable information terminal, a mobile computer, and a cellulartelephone.
 77. A device according to claim 68 , wherein each of saidportions of the interlayer insulating film is exposed in a gap betweentwo adjacent pixel electrodes.